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ML610482 - 8-bit Microcontroller

Download the ML610482 datasheet PDF. This datasheet also covers the ML610Q482 variant, as both devices belong to the same 8-bit microcontroller family and are provided as variant models within a single manufacturer datasheet.

General Description

This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), buzzer driver, battery level detect circuit, and RC oscillation type A/D converter, are incorporated around 8-bit CPU nX-U8/100.

Key Features

  • CPU.
  • 8-bit RISC CPU (CPU name: nX-U8/100).
  • Instruction system: 16-bit instructions.
  • Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on.
  • On-Chip debug function (ML610Q482).
  • Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 0.244µs (@4.096 MHz sys.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ML610Q482-LAPISSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ML610482
Manufacturer LAPIS Semiconductor
File Size 458.72 KB
Description 8-bit Microcontroller
Datasheet download datasheet ML610482 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ML610Q482/ML610482 8-bit Microcontroller FEDL610Q482-02 Issue Date: May.9, 2014 GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), buzzer driver, battery level detect circuit, and RC oscillation type A/D converter, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications.